Data path circuit design using reinforcement learning
US12387028B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 2, 2021 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Feb 1, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.