Gate driving circuit and display apparatus including the same
US12387687B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Dec 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit that prevents the discharge of the Q node due to the leakage current in the last stage when the panel is cut, thereby preventing distortion of the gate signal, and a display including the same is disclosed. The gate driving circuit includes a plurality of stages driving a plurality of gate lines, and each of the plurality of stages includes a pull-up transistor pull-up driving an output terminal in response to a signal of a Q node of a N stage; a pull-down transistor pull-down driving an output terminal in response to a signal of a Qb node of the N stage; and a first transistor coupled between a source electrode of the pull-down transistor and a Q node of a N−1 stage, and pull-down driving the Q node of the N−1 stage in response to a signal of the output terminal of the N stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.