Memory device for supporting new command input scheme and method of operating the same
US12387771B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2024 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | May 3, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.