Method for optimizing flash memory chip and related apparatus
US12387809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Feb 7, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a method for optimizing a flash memory chip and a related apparatus. The method comprises, after completing write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point that triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the trigger condition is related to working environmental data of the NFI; upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes a margin test; and upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI. In this way, the NFI bus channels can be optimized without disk disconnection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.