Memory devices and electronic devices outputting event data related to occurrences of errors and operating methods of memory devices
US12387810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Oct 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.