Semiconductor test structure and method for manufacturing same
US12387938B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Mar 9, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor test structure and a method for manufacturing the same are provided. The method for manufacturing a semiconductor test structure includes providing a semiconductor structure, which includes a doped layer and a metal layer located in the doped layer; forming at least one opening exposing the metal layer in the semiconductor structure; removing the metal layer by a reaction between a wet etching solution and the metal to form a hollow portion, in which the wet etching solution enters the semiconductor structure through the opening; and filling the hollow portion with a non-metallic material layer through the opening to form the semiconductor test structure, in which an evaporation pressure of the metal layer is greater than an evaporation pressure of the non-metallic material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.