Semiconductor package including redistribution pattern
US12388000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Oct 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1533
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip including a connecting pad, a mold layer covering the semiconductor chip, a lower redistribution layer on the semiconductor chip and the mold layer, and a connecting terminal on the lower redistribution layer. The lower redistribution layer includes a first lower insulating layer, a first conformal redistribution pattern extending through the first lower insulating layer, a second lower insulating layer on the first lower insulating layer and the first conformal redistribution pattern, and a first filled redistribution pattern disposed on the first conformal redistribution pattern and extending through the second lower insulating layer. A side surface of the first filled redistribution pattern is spaced apart from an inner side surface of the first conformal redistribution pattern. The second lower insulating layer is between the inner side surface of the first conformal redistribution pattern and the side surface of the first filled redistribution pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.