Retention flip-flop with multiple positive supply voltage domains
US12388427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Mar 11, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A disclosed flip-flop includes primary and secondary sections connected to switchable and continuous power supplies, respectively. The primary section includes logic outputting first control signals, a primary latch controlled by the first control signals, and a data output device connected to an output terminal of the primary latch. The secondary section includes logic outputting second control signals and a secondary latch. A first transmission gate controlled by the second control signals is connected between the output terminal of the primary latch and an input terminal of the secondary latch. A second transmission gate controlled by the first and second control signals is connected between output and input terminals of the secondary latch. In a normal mode, both sections receive power and the first transmission gate is conductive. In a retention mode, the primary section is powered down, the first transmission gate is non-conductive and the second transmission gate is conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.