Subranging ADC buffer cascade
US12388460B2 · kind B2 · utility
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13References
20Claims
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Key dates
| Filing date | Jun 6, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) system, such as a subranging ADC, including a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, buffer circuits can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.