Timer-based resolver integral demodulation

US12388461B2 · kind B2 · utility

Assignee

• Hamilton Sundstrand Corporation (HSC) · US

Inventors

• Divya Nagaraju · Survanagiri, IN
• Ashish Vijay · Gothan, IN
• Sundaram Kaliyugavaratharajan · Survanagiri, IN
• Kannan Thiagarajan · Survanagiri, IN

Key dates

• Filing date: Jul 7, 2023
• Grant date: Aug 12, 2025
• Expiry date: Feb 18, 2044

Classification

• Technology area (CPC G): Physics
• CPC primary: G01D5/2073
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.