Pretap equalizable continuous time linear equalizer
US12388688B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2023 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Nov 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/01
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit includes first, second, third, and fourth transistors, and a capacitor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, second terminal, and a control terminal. The capacitor has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor has a first terminal coupled to the first terminal of the second transistor, a second terminal, and a control terminal coupled to the control terminal of the first transistor. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the third transistor, and a control terminal coupled to the control terminal of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.