Method of fabricating a semiconductor memory device
US12389585B2 · kind B2 · utility
0Cited by
7References
13Claims
0Family size
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Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Dec 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.