Semiconductor structure and fabrication method thereof
US12389651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Nov 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a semiconductor structure and a fabrication method. The method includes: providing a substrate, where a first trench is formed in the substrate; forming a first dielectric layer and a protective material layer in the first trench, where the first dielectric layer is positioned between the protective material layer and the substrate, and an upper surface of the first dielectric layer is lower than an upper surface of the substrate, to expose a portion of a side wall of the first trench; forming a second dielectric layer on the exposed side wall of the first trench; and filling the second trench to form a work function structure, where the work function structure includes a first work function layer and a second work function layer, where the second work function layer is positioned on an upper surface of the first work function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.