Semiconductor device including backside contact structure with silicide layer formed in FEOL process
US12389660B1 · kind B1 · utility
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14Claims
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Key dates
| Filing date | Aug 19, 2024 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Aug 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device including backside contact structure with a silicide layer formed in an FEOL process, and a method of manufacturing the same. The method includes: forming a channel structure on a substrate; forming a placeholder structure in the substrate; forming a silicide layer on the placeholder structure; forming a source/drain region on the silicide layer based on the channel structure; forming a gate structure on the channel structure; and forming a backside contact structure on a bottom surface of the placeholder structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.