Cooling device semiconductor device including end curved interconnection lines
US12389676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jul 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/985
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.