Solid-state imaging device and electronic apparatus
US12389706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2024 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | May 20, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F99/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line another wiring layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.