Method for fabricating a semiconductor device including integrating III-V device and CMOS device, and the semiconductor device thereof
US12389718B2 · kind B2 · utility
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9References
12Claims
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Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Jun 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/857
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device (200) is described. According to a described embodiment, the method comprises: (i) forming a III-V semiconductor material layer (206) comprising a substrate layer (208) and a device layer (210) attached to the substrate layer (208); and (ii) forming an electrically conductive interlayer (228) to the device layer (210) prior to bonding the electrically conductive interlayer (228) to a partially processed CMOS device layer (204) having at least one transistor (205).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.