Stand-by circuit
US12393219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Mar 14, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A III-nitride power semiconductor based heterojunction device comprising a substrate, a first terminal, a second terminal, a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation, and an active heterojunction transistor formed on the substrate. The device further comprises a stand-by signal generation circuit configured to generate a stand-by signal when the input switching signal to the control terminal has not been detected for a set period of time, at least one Miller clamp transistor and driving circuitry associated with the at least one Miller clamp transistor, a voltage regulator circuit configured to provide at least a low power consumption output and a high power consumption output, wherein the low power consumption output is enabled at least during the stand-by mode of operation and the high power consumption output is disabled by the stand-by signal during the stand-by mode of operation, and a rail voltage terminal configured to provide an input to the voltage regulator circuit. The low power consumption output is provided to the driving circuitr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.