System and a method for network-on-chip power management
US12393255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Mar 26, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a system for network-on-chip power management. The system comprising a primary network-on-chip comprises multiple components, each component having a power controller, characterized by a secondary network-on-chip comprises a secondary network-on-chip master node and a plurality of secondary network-on-chip nodes connected thereto, the plurality of secondary network-on-chip nodes associated to the components of the primary network-on-chip for power managing individual and link components of the primary network-on-chip, and a power management unit connected to the secondary network-on-chip master node, configured to polling status registers of the components of the primary network-on-chip for accessing power states of each component, accessing routing information of the components of the primary network-on-chip and sending request to the secondary network-on-chip nodes for powering on or off the associated components of the primary network-chip through the power controller. A method for network-on-chip power management is also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.