Wake-up management circuit for multiple processors
US12393258B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Aug 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wake-up management circuit for implementation in circuit boards with multiple processors is disclosed. The wake-up management circuit utilizes hardware resources to generate a wake-up signal for a processor in a low power mode when traffic intended for the processor is received by the wake-up management circuit. The wake-up management circuit is configured to generate a wake-up signal for a specific processor when address information in a data packet received by the wake-up management circuit indicates that the data packet is intended for the specific processor (e.g., the specific processor is the destination for the data packet).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.