Memory device, memory system including the same and method of operating the same
US12394466B2 · kind B2 · utility
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24References
20Claims
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Key dates
| Filing date | May 18, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Aug 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including a plurality of memory cells coupled to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array, a register configured to store a weighted access count for each of a plurality of row addresses; an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, and a calculator configured to calculate the access spacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.