Interface of a memory circuit
US12394473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Jan 11, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage. The at least one data terminal receives a first data signal that varies between a second high voltage and the low voltage during a command phase, and transmits or receives a second data signal during a data phase. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and transmits or receives a second data strobe signal that swings periodically during the data phase. During a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.