Semiconductor memory device and manufacturing method thereof
US12394482B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Aug 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes: a first chip including first conductive layers arranged at intervals in a first direction, a first semiconductor layer extending through an inside of the first conductive layers in the first direction, a first insulating film between the first semiconductor layer and the first conductive layers, a second semiconductor layer provided above the first conductive layers and in contact with the first semiconductor layer, and a first electrode provided in contact with an upper side of the second semiconductor layer; and a second chip including a second electrode in contact with the first electrode, and a second conductive layer in contact with the second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.