Correlated orbitals yield high-mobility, back-end-of-line compatible p-type oxide semiconductor
US12394622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Mar 7, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02631
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments disclosed herein provide for several methods of fabricating p-type semiconductors with industrially relevant hole mobilities that are back end of the line (BEOL) compatible. A first method of fabrication includes forming a buffer layer on a substrate, forming a palladium oxide layer over the buffer layer, annealing the palladium oxide layer, and then forming a cap layer over the palladium oxide layer, then cooling the stack, wherein each step is performed at a variety of predefined temperatures. Each of the substrate, buffer layer and cap layer can be magnesium oxide. A second method includes forming a palladium oxide layer over a titanium dioxide substrate, annealing the stack, and then cooling the stack, all performed at a different variety of predefined temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.