Patent · US Active

Layout design of custom stack capacitor to procure high capacitance

US12394705B2 · kind B2 · utility

0Cited by

2References

10Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Prakash Rattaisutripalayam Palanisamy · Kanchinakote, IN
Bruce Lee · Irvine, US
Bavireddy Sai Krishna · Guntur, IN
Balavva Shivappa Kamatagi · Bailahongala, IN

Key dates

Filing date	Aug 15, 2022
Grant date	Aug 19, 2025
Priority date	—
Expiry date	Oct 17, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/813
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip includes a first capacitor. The first capacitor includes first electrodes formed from metal layer M0, wherein the first electrodes are coupled to one another. The first capacitor also includes second electrodes formed from the metal layer M0, wherein the second electrodes are coupled to one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.