Apparatus and methods to control well bias in a semiconductor device
US12395165B2 · kind B2 · utility
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1References
22Claims
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Key dates
| Filing date | Oct 31, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Feb 23, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example circuit includes a substrate including a first transistor of a gate driver output stage, the substrate including a first well region; a diode circuit including a first terminal and a second terminal, the first terminal coupled to a first tap of the first well region; and a second transistor including a first terminal, a second terminal, and a body, the first terminal of the second transistor coupled to a switching voltage terminal, and the second terminal and the body of the second transistor coupled to the first tap of the first well region and to the first terminal of the diode circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.