Preparation method for semiconductor structure, semiconductor structure and semiconductor memory
US12396157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2022 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Oct 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6728
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.