Integrated circuit device
US12396224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2023 |
| Grant date | Aug 19, 2025 |
| Priority date | — |
| Expiry date | Dec 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/251
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.