Memory device
US12399644B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 26, 2024 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Feb 26, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.