Memory multichip package employing a frequency multiplying bridge chip
US12399652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2024 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Mar 8, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first interface with a first channel at a first data transfer rate, a second interface with a second channel at a second data transfer rate slower than the first data transfer rate, a transfer circuit, and a processor. The processor is configured to, upon the first interface receiving a first data output command from a memory controller via the first channel, issue the first data output command via the second channel, in response to which a first memory chip connected to the second interface reads first data corresponding to the first data output command, and after a first predetermined amount of time has elapsed from the issuance of the first data output command, issue a first transfer start command via the second channel, in response to which the first data is transferred to the transfer circuit via the second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.