Multiplier, multiply-accumulate circuit, and convolution operation unit
US12399686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2024 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 19, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.