Global monitor for multi-port memory controller
US12399844B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2024 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Feb 28, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus includes: a fabric circuit to couple between a plurality of managers and a memory; and multi-bank memory control circuitry coupled to the fabric circuit and to couple to a plurality of banks of the memory and including a plurality of first ports to receive memory requests from the plurality of managers, The multi-bank memory control circuitry is to enable each of the plurality of managers to access the memory in parallel. A global monitor is coupled to the multi-bank memory control circuitry and includes a plurality of second ports and a plurality of state machines, each of the plurality of state machines to be associated with one of the plurality of managers. Each of the plurality of state machines is configured to enforce exclusivity of a memory region on behalf of a manager and concurrently enable non-exclusive access to the memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.