Method, system, medium and program for clock design of physical partition structure
US12400058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 15, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock design method for two or more physical partition structures based on a same system clock. The method includes determining a distance of each circuit logic from the system clock; based on the distance between each circuit logic and the system clock, obtaining a plurality of clock nodes from the system clock to cause a delay of each clock node compared to the system clock to change with the distance from each circuit logic and the system clock, the greater the distance, the greater the delay; connecting each circuit logic to a corresponding clock node based on size of each circuit logic and the distance; and converging timing of each circuit logic by adjusting the delay of each clock node compared to the system clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.