Memory device and method for training per-pin operation parameters
US12400691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Feb 29, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a memory device and a method for training per-pin operation parameters. A memory device includes a plurality of on-die termination (ODT) circuits, an impedance control (ZQ) calibration circuit configured to output a first code signal and a second code signal, and a per-pin calibration circuit. The per-pin calibration circuit may be configured to select one signal pin from among the plurality of signal pins, to compare a first input voltage level of the selected signal pin with a second input voltage level of each of the other ones of the plurality of signal pins, to generate a per-pin ODT code signal for each of the plurality of signal pins, to combine the per-pin ODT code signal with the first code signal or the second code signal, and to provide the combined per-pin ODT code signal to the respective ODT circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.