Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering
US12400700B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 11, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a memory device comprising: —DRAM memory circuits (100), the total capacity of which is divided into a first part (102) and a second part (103) larger than the first part (102); —a control circuit configured to access the memory circuits, the control circuit comprising: —a first block (201) configured to execute a first algorithm (201A) intended to protect the first part (102) from a row-hammering effect; —a second block (202) configured to execute a second algorithm (202A) intended to protect the second part (103) from a row-hammering effect that may occur, the second algorithm (202A) using a main table stored in the first part (102).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.