Semiconductor memory device and method of operating semiconductor memory device
US12400729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Nov 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.