Geometric semiconductor memory structure and manufacturing method thereof
US12400957B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 24, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Dec 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, having a first surface; a plurality of memory cells, located on the first surface of the substrate and arranged according to a first preset pattern; and a plurality of memory contact structures, corresponding to the memory cells in a one-to-one manner, where bottom portions of the memory contact structures are in contact with top portions of the memory cells, and top portions of the memory contact structures are arranged according to a second preset pattern. The bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.