Chip package on package structure, packaging method thereof, and electronic device
US12400982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Oct 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package on package structure includes a primary chip stack unit having pins insulated and spaced from each other on a first surface; a first bonding layer disposed on the first surface, where the first bonding layer includes bonding components insulated and spaced from each other, each bonding component includes a bonding part, and any two bonding parts are insulated and have a same cross-sectional area, and the bonding components are separately bonded to the pins; and secondary chip stack units, disposed on a surface of a side that is of the first bonding layer and that is away from the primary chip stack unit, where the secondary chip stack unit has micro bumps insulated and spaced from each other, and each of the micro bumps is bonded to one of the bonding components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.