PFC optimization architecture for ac input AC/DC switching mode power supplies
US12401270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | May 23, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An AC input AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises a boost follower circuit (BFC), a hybrid bulk capacitance circuit (HBCC) and driver and control circuitry. The BFC senses the peak AC input voltage and adjusts a PFC output voltage Vdc dependent on the AC input voltage, to improve low line efficiency and reduce losses. The BFC may provide a stepless or step regulation mode to follow the AC input line voltage. The driver and control circuitry coordinates operation of the BFC and HBCC. The driver and control circuitry comprises comparator circuitry, which enables selective connection of bulk capacitors of different voltage ratings, responsive to a sense voltage from the BFC, to meet requirements for ripple voltage and hold-up times for different Vdc. This solution provides a reduction in capacitor height and volume, with associated improvement in the power density of an isolated AC/DC power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.