PUF circuit based on threshold loss of MOSFETs
US12401362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | May 24, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.