Calibration of digital-to-analog converters
US12401371B2 · kind B2 · utility
0Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Oct 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.