Output array for RF performance improvement
US12401381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Sep 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0416
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier output stage includes a first output array group having a first plurality of semiconductor devices, and a first loading adjustment module coupled to the first output array group. The first loading adjustment module is configured to adjust a loading of the first output array group to produce a first power dissipation value associated with the first output array group. The power amplifier output stage further includes a second output array group having a second plurality of semiconductor devices, and a second source loading adjustment module coupled to a second input of the second output array. The second source loading adjustment module is configured to adjust a source loading of the second output array group to produce a second power dissipation value associated with the second output array group, the first power dissipation value being different from the second power dissipation value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.