Clock and data recovery circuit and a display apparatus having the same
US12401489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Jun 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.