Dynamic voltage and frequency scaling for image-sensor applications
US12401921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Sep 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/7795
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging device having a digital circuit block therein subjected to in-frame DVFS during a frame sequence of the sensing operating mode. In an example embodiment, the in-frame DVFS causes a higher power-supply voltage and a higher clock frequency to be supplied to the digital circuit block during read periods of the frame sequence, and a lower power-supply voltage and a lower clock frequency to be supplied to the digital circuit block during V-blanking periods of the frame sequence. The lower power-supply voltage and clock frequency are selected to be sufficient for the digital circuit block to support the pertinent functions thereof during the V-blanking periods without adversely impacting performance. For example, the lower power-supply voltage is sufficient for a SRAM of the digital circuit block to retain data therein. Beneficially, the in-frame DVFS enables the imaging device to perform motion detection while consuming very little power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.