Power via resonance suppression
US12402251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Apr 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0207
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.