Three-dimensional semiconductor memory devices
US12402314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2023 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Dec 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.