Vertical channel semiconductor device with ferroelectric-insulator gate stack
US12402321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Aug 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/40
Abstract
A semiconductor device includes a plurality of first conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the first direction and second direction being horizontal directions, a plurality of vertical semiconductor patterns disposed on the plurality of first conductive lines, respectively, a gate electrode crossing the plurality of first conductive lines and penetrating each of the plurality of vertical semiconductor patterns, a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns, and a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.