Array substrate and manufacturing method thereof
US12402481B2 · kind B2 · utility
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Key dates
| Filing date | Apr 26, 2024 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Apr 26, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/123
Abstract
An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate and a first recess. The first recess sequentially extends through a second inorganic layer, a third insulating layer, a first inorganic layer, a second insulating layer, a first insulating layer, a first semiconductor layer, and a portion of a barrier layer. A bottom surface of the first recess is formed inside the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.