Patent · US Active

Scalarization of instructions for SIMT architectures

US12405801B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

NVIDIA Corporation · US

Inventors

Aditya Avinash Atluri · Redmond, US
Jack Choquette · Palo Alto, US
Carter Edwards · Campbell, US
Olivier Giroux · Santa Clara, US
Praveen Kumar Kaushik · Survanagiri, IN
Ronny Meir Krashinsky · San Francisco, US
Rishkul Kulkarni · Austin, US
Konstantinos Kyriakopoulos · Weinsberg, DE

Key dates

Filing date	Feb 3, 2023
Grant date	Sep 2, 2025
Priority date	—
Expiry date	Aug 15, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3851
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a set of one or more threads is selected from a group of active threads associated with an instruction and the instruction is executed for the set of one or more threads on a serial execution unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.