Hardware unit for performing matrix multiplication with clock gating
US12405804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Apr 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Matrix multiplication via a multi-stage pipeline is performed wherein storage elements associated with stages of the pipeline are clock-gated based on data elements thereof known to have or treatable as having a zero value. The storage elements may be clock-gated on a per data element basis based on whether the data element has or can be treated as having a zero value. The storage elements alternatively may be clock-gated on a partial element basis based on the bit width of the data elements. For example, if the bit width of the data elements is less than a maximum bit width then bits related to that data element can be treated as having a zero value and storage elements associated with that data element may not be clocked. In yet other cases the storage elements may be clock-gated on both a per element and a partial element basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.